Why does it seem like the JTAG clock signal is active low? Consider this snippet from Xilinx’s XAPP058 source code.
/* toggle tck LH. No need to modify this code. It is output via setPort. /
setPort(TCK,0); / set the TCK port to low /
setPort(TCK,1); / set the TCK port to high */
This means that when the clock isn’t being pulsed, it’s high. Right? If so, why don’t any descriptions of JTAG’s electrical characteristics say it’s active low?